View HFA1113ML883_1163131.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

189 tm hfa1113/883 output limiting, ultra high speed programmable gain, buffer amplifier description the hfa1113/883 is a closed loop buffer featuring a high degree of gain accuracy, wide bandwidth, low distortion, and programmable output limiting. this buffer is the ideal choice for high frequency applications requiring output limiting, especially those needing ultra fast overdrive recovery times. the output limiting function allows the designer to set the maximum positive and negative output levels, thereby pro- tecting later stages from damage or input saturation. the sub-nanosecond overdrive recovery time quickly returns the amplifier to linear operation following an overdrive condition. component and composite video systems will also benefit from this buffer?s performance, as indicated by the excellent gain flatness, and 0.02%/0.04 deg. differential gain/phase specifications (r l =150 ? ). a unique feature of the pinout allows the user to select a voltage gain of +1, -1, or +2, without the use of any external components, as described in the ?design information? sec- tion. compatibility with existing op amp pinouts provides flexibility to upgrade low gain amplifiers, while decreasing component count. unlike most buffers, the standard pinout provides an upgrade path should a higher closed loop gain be needed at a future date. this amplifier is available without output limiting as the hfa1112/883. for applications requiring a standard buffer pinout, please refer to the hfa1110/883 datasheet. ordering information part number temperature range package hfa1113mj/883 -55 o c to +125 o c 8 lead cerdip hfa1113ml/883 -55 o c to +125 o c 20 lead ceramic lcc features ? this circuit is processed in accordance to mil-std- 883 and is fully conformant under the provisions of paragraph 1.2.1. ? user programmable output voltage limiting ? user programmable for closed-loop gains of +1, -1 or +2 without use of external resistors ? low differential gain and phase . . . . .0.02%/0.04 deg. ? low distortion (hd3, 30mhz) . . . . . . . . . . -73dbc (typ) ? wide -3db bandwidth . . . . . . . . . . . . . . . 850mhz (typ) ? very high slew rate . . . . . . . . . . . . . . . 2400v/ s (typ) ? fast settling (0.1%) . . . . . . . . . . . . . . . . . . . . 13ns (typ) ? excellent gain flatness (to 100mhz) . . . . 0.07db (typ) ? excellent gain accuracy . . . . . . . . . . . . . . 0.99v/v (typ) ? high output current . . . . . . . . . . . . . . . . . . 60ma (typ) ? fast overdrive recovery . . . . . . . . . . . . . . . <1ns (typ) applications ? video switching and routing ? pulse and video amplifiers ? wideband amplifiers ? rf/if signal processing ? flash a/d driver ? medical imaging systems july 1994 pinouts hfa1113/883 (cerdip) top view hfa1113/883 (clcc) top view nc -in +in v- 1 2 3 4 8 7 6 5 v h v+ out v l 300 300 + - 4 5 6 7 8 9101112 13 32 12019 15 14 18 17 16 nc nc nc nc nc nc nc nc nc nc nc nc nc v- v l -in +in out v+ v h 300 + - 300 spec number 511106-883 fn3618.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
190 specifications hfa1113/883 absolute maximum ratings thermal information voltage between v+ and v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v voltage at either input terminal . . . . . . . . . . . . . . . . . . . . . . v+ to v- voltage at v h or v l terminal . . . . . . . . . . . . . (v+) + 2v to (v-) - 2v output current (50% duty cycle) . . . . . . . . . . . . . . . . . . . . . . . . 55ma junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c esd rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . < 2000v storage temperature range . . . . . . . . . . . . . . -65 o c t a +150 o c lead temperature (soldering 10s). . . . . . . . . . . . . . . . . . . . +300 o c thermal resistance ja jc cerdip package . . . . . . . . . . . . . . . . . 115 o c/w 30 o c/w ceramic lcc package . . . . . . . . . . . . 75 o c/w 23 o c/w maximum package power dissipation at +75 o c cerdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.87w ceramic lcc package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.33w package power dissipation derating factor above +75 o c cerdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7mw/ o c ceramic lcc package . . . . . . . . . . . . . . . . . . . . . . . . 13.3mw/ o c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. operating conditions operating supply voltage ( v s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v operating temperature range. . . . . . . . . . . . .-55 o c t a +125 o c r l ? 50 ? table 1. dc electrical performance characteristics device tested at: v supply = 5v, r source =0 ? , r l =100 ? , v out = 0v, unless otherwise specified. parameters symbol conditions group a subgroups temperature limits units min max output offset voltage v os v cm =0v 1 +25 o c-2525mv 2, 3 +125 o c, -55 o c-4040mv power supply rejection ratio psrrp ? v supply = 1.25v, v+=6.25v, v-=-5v, v+=3.75v, v-=-5v 1+25 o c39-db 2, 3 +125 o c, -55 o c35 -db psrrn ? v supply = 1.25v, v+ = 5v, v- = -6.25v, v+ = 5v, v- = -3.75v 1+25 o c39-db 2, 3 +125 o c, -55 o c35 -db non-inverting input (+in) current i bsp v cm =0v 1 +25 o c-4040 a 2, 3 +125 o c, -55 o c-6565 a +in common mode rejection cms ibp ? v cm = 2v, v+ = 3v, v- = -7v, v+ = 7v, v- = -3v 1+25 o c-40 a/v 2, 3 +125 o c, -55 o c-50 a/v +in resistance +r in note 1 1 +25 o c25-k ? 2, 3 +125 o c, -55 o c20 -k ? gain (v out =2v p-p )a vp1 a v =+1, v in = -1v to +1v 1+25 o c 0.980 1.020 v/v 2, 3 +125 o c, -55 o c 0.975 1.025 v/v gain (v out =2v p-p )a vm1 a v =-1, v in = -1v to +1v 1+25 o c 0.980 1.020 v/v 2, 3 +125 o c, -55 o c 0.975 1.025 v/v gain (v out =4v p-p )a vp2 a v =+2, v in = -1v to +1v 1+25 o c 1.960 2.040 v/v 2, 3 +125 o c, -55 o c 1.950 2.050 v/v output voltage swing v op100 a v =-1 r l =100 ? v in = -3.2v 1 +25 o c3-v v in =- 2.7v 2, 3 +125 o c, -55 o c2.5 - v v on100 a v =-1 r l =100 ? v in = +3.2v 1 +25 o c--3v v in = +2.7v 2, 3 +125 o c, -55 o c--2.5v output voltage swing v op50 a v =-1 r l =50 ? v in = -2.7v 1, 2 +25 o c, +125 o c2.5 - v v in =- 2.25v 3-55 o c1.5-v v on50 a v =-1 r l =50 ? v in = +2.7v 1, 2 +25 o c, +125 o c--2.5v v in =+2.25v 3 -55 o c--1.5v spec number 511106-883
191 specifications hfa1113/883 output current +i out note 2 1, 2 +25 o c, +125 o c50 -ma 3-55 o c30-ma -i out note 2 1, 2 +25 o c, +125 o c--50ma 3-55 o c--30ma quiescent power supply current i cc r l =100 ? 1+25 o c1426ma 2, 3 +125 o c, -55 o c-33ma i ee r l =100 ? 1+25 o c-26-14ma 2, 3 +125 o c, -55 o c-33 - ma limiting accuracy v h clmp a v =-1, v in =-1.6v, v h =1v 1+25 o c -150 150 mv 2, 3 +125 o c, -55 o c -200 200 mv v l clmp a v =-1, v in = +1.6v, v l =-1v 1+25 o c -150 150 mv 2, 3 +125 o c, -55 o c -200 200 mv v h or v l input current v h bias v h =1v 1 +25 o c-200 a 2, 3 +125 o c, -55 o c-300 a v l bias v l = -1v 1 +25 o c-200- a 2, 3 +125 o c, -55 o c-300 - a notes: 1. guaranteed from +in common mode rejection test, by: +r in =1/cms ibp . 2. guaranteed from v out test with r l =50 ? , by: i out =v out /50 ?. table 2. ac electrical performance characteristics table 2 intentionally left blank. table 3. electrical performance characteristics device characterized at: v supply = 5v, r l =1 00? , unless otherwise specified. parameters symbol conditions notes temperature limits units min max -3db bandwidth bw(-1) a v =-1, v out = 200mv p-p 1+25 o c450-mhz bw(+1) a v =+1, v out = 200mv p-p 1+25 o c500-mhz bw(+2) a v =+2, v out = 200mv p-p 1+25 o c350-mhz gain flatness gf30 a v =+2, f 30mhz, v out = 200mv p-p 1+25 o c- 0.04 db gf50 a v =+2, f 50mhz, v out = 200mv p-p 1+25 o c- 0.08 db gf100 a v =+2, f 100mhz, v out = 200mv p-p 1+25 o c- 0.22 db slew rate +sr(-1) a v =-1, v out = 5v p-p 1, 2 +25 o c1500-v/ s -sr(-1) a v =-1, v out = 5v p-p 1, 2 +25 o c1800-v/ s +sr(+1) a v =+1, v out = 5v p-p 1, 2 +25 o c900-v/ s -sr(+1) a v =+1, v out = 5v p-p 1, 2 +25 o c800-v/ s +sr(+2) a v =+2, v out = 5v p-p 1, 2 +25 o c1200-v/ s -sr(+2) a v =+2, v out = 5v p-p 1, 2 +25 o c1100-v/ s table 1. dc electrical performance characteristics (continued) device tested at: v supply = 5v, r source =0 ? , r l =100 ? , v out = 0v, unless otherwise specified. parameters symbol conditions group a subgroups temperature limits units min max spec number 511106-883
192 specifications hfa1113/883 rise and fall time t r (-1) a v =-1, v out = 0.5v p-p 1, 2 +25 o c-750ps t f (-1) a v =-1, v out = 0.5v p-p 1, 2 +25 o c-800ps t r (+1) a v =+1, v out = 0.5v p-p 1, 2 +25 o c-750ps t f (+1) a v =+1, v out = 0.5v p-p 1, 2 +25 o c-750ps t r (+2) a v =+2, v out = 0.5v p-p 1, 2 +25 o c - 1000 ps t f (+2) a v =+2, v out = 0.5v p-p 1, 2 +25 o c - 1000 ps overshoot +os(-1) a v =-1, v out = 0.5v p-p 1, 3 +25 o c-30% -os(-1) a v =-1, v out = 0.5v p-p 1, 3 +25 o c-25% +os(+1) a v =+1, v out = 0.5v p-p 1, 3 +25 o c-65% -os(+1) a v =+1, v out = 0.5v p-p 1, 3 +25 o c-60% +os(+2) a v =+2, v out = 0.5v p-p 1, 3 +25 o c-20% -os(+2) a v =+2, v out = 0.5v p-p 1, 3 +25 o c-20% settling time ts(0.1) a v = +2, to 0.1%, v out = 2v to 0v 1+25 o c - 20 ns ts(0.05) a v = +2, to 0.05%, v out = 2v to 0v 1+25 o c - 33 ns 2nd harmonic distortion hd2(30) a v =+2, f=30mhz, v out = 2v p-p 1+25 o c--45dbc hd2(50) a v =+2, f=50mhz, v out = 2v p-p 1+25 o c--40dbc hd2(100) a v = +2, f = 100mhz, v out = 2v p-p 1+25 o c--35dbc 3rd harmonic distortion hd3(30) a v =+2, f=30mhz, v out = 2v p-p 1+25 o c--65dbc hd3(50) a v =+2, f=50mhz, v out = 2v p-p 1+25 o c--55dbc hd3(100) a v = +2, f = 100mhz, v out = 2v p-p 1+25 o c--45dbc notes: 1. parameters listed in table 3 are controlled via design or process parameters and are not directly tested at final production. these param- eters are lab characterized upon initial design release, or upon design changes. these parameters are guaranteed by characteriz ation based upon data from multiple production runs which reflect lot-to-lot and within lot variation. 2. measured between 10% and 90% points. 3. for 200ps input transition times. overshoot decreases as input transition times increase, especially for a v = +1. please refer to performance curves. table 4. electrical test requirements mil-std-883 test requirements subgroups (see table 1) interim electrical parameters (pre burn-in) 1 final electrical test parameters 1 (note 1), 2, 3 group a test requirements 1, 2, 3 groups c and d endpoints 1 note: 1. pda applies to subgroup 1 only. table 3. electrical performance characteristics (continued) device characterized at: v supply = 5v, r l =1 00? , unless otherwise specified. parameters symbol conditions notes temperature limits units min max spec number 511106-883
193 hfa1113/883 die characteristics die dimensions: 63 x 44 x 19 mils 1 mils 1600 x 1130 x 483 m 25.4 m metallization: type: metal 1: aicu(2%)/tiw type: metal 2: aicu(2%) thickness: metal 1: 8k ? 0.4k ? thickness: metal 2: 16k ? 0.8k ? glassivation: type: nitride thickness: 4k ? 0.5k ? worst case current density: 2.0 x 10 5 a/cm 2 at 47.5ma transistor count: 52 substrate potential (powered up): floating (recommend connection to v-) metallization mask layout hfa1113/883 nc v- v l nc out +in -in v h v+ spec number 511106-883
194 hfa1113/883 test circuit (applies to table 1) test waveforms simplified test circuit for large and small signal pulse response (applies to table 3) a v = +1 or +2 test circuit a v = -1 test circuit large signal waveform small signal waveform v+ i cc 10 0.1 7 dut - + 2 3 4 - + ha-5177 100k (0.01%) v z +i bias = v z 100k 10 0.1 v- i ee 510 - + v y = v os v y 100 k3 k1 100 100 v out 470pf x100 6 + + 0.1 0.1 1k 510 0.1 0.1 +v in k2 -v in nc 1 2 1 2 50 k3 5 8 v h 0.1 nc v l 0.1 0.1 nc k4 0.1 50 note: terminal numbers refer to cerdip package all resistors = 1% ( ? ) all capacitors = 10% ( f) unless otherwise noted chip components recommended for a v = +1, k1 = position 1, k2 = position 1 for a v = +2, k1 = position 1, k2 = position 2, -v in =0v for a v = -1, k1 = position 1, k2 = position 2, +v in =0v - + v in r s 50 ? v out v+ v- 50 ? 50 ? r g 2 3 2 7 4 6 note: v s = 5v, r g =0 ? for a v =+2, r g = for a v =+1 r f = internal, r s =50 ? r l =100 ? for small and large signals terminal numbers refer to cerdip package + - v in r s 50 ? v out v+ v- 50 ? 50 ? 2 2 3 7 4 6 note: v s = 5v, a v =-1 r f = internal r s =50 ?, r l =100 ? for small and large signals terminal numbers refer to cerdip package 90% 10% 90% 10% +2.5v -sr +2.5v +sr v out -2.5v -2.5v 90% 10% 90% 10% +250mv t f , -os +250mv t r , +os v out -250mv -250mv spec number 511106-883
195 hfa1113/883 burn-in circuits hfa1113mj/883 ceramic dip hfa1113ml/883 ceramic lcc 1 2 3 4 8 7 6 5 v+ c1 d1 d2 c2 v- nc d4 d3 r1 notes: r1 = 100 ? , 5% (per socket) c1 = c2 = 0.01 f (per socket) or 0.1 f (per row) minimum d1 = d2 = 1n4002 or equivalent (per board) d3 = d4 = 1n4002 or equivalent (per socket) v+ = +5.5v 0.5v v- = -5.5v 0.5v 300 + - 300 v+ c1 d1 d2 v- d4 d3 r1 4 5 6 7 8 9101112 13 32 12019 15 14 18 17 16 c2 r2 nc notes: r1 = 1k ? , 5% (per socket) r2 = 100 ? , 5% (per socket) c1 = c2 = 0.01 f (per socket) or 0.1 f (per row) minimum d1 = d2 = 1n4002 or equivalent (per board) d3 = d4 = 1n4002 or equivalent (per socket) v+=+5.5v 0.5v v- = -5.5v 0.5v 300 + - 300 spec number 511106-883
196 hfa1113/883 f8.3a mil-std-1835 gdip1-t8 (d-4, config uration a) 8 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.405 - 10.29 5 e 0.220 0.310 5.59 7.87 5 e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n8 88 rev. 0 4/94 notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this configuration dimension b3 replaces dimension b2. 5. this dimension allows for off-center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. 11. materials: compliant to mil-i-38535. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a ceramic dual-in-line frit seal packages (cerdip) spec number 511106-883
197 hfa1113/883 d j x 45 o d3 b h x 45 o a a1 e l l3 e b3 l1 d2 d1 e 1 e2 e1 l2 plane 2 plane 1 e3 b2 0.010 e h s s 0.010 e f s s -e- 0.007 e f m s h s b1 -h- -f- j20.a mil-std-1835 cqcc1-n20 (c-2) 20 pad leadless ceramic chip carrier symbol inches millimeters notes min max min max a 0.060 0.100 1.52 2.54 6, 7 a1 0.050 0.088 1.27 2.23 - b----- b1 0.022 0.028 0.56 0.71 2, 4 b2 0.072 ref 1.83 ref - b3 0.006 0.022 0.15 0.56 - d 0.342 0.358 8.69 9.09 - d1 0.200 bsc 5.08 bsc - d2 0.100 bsc 2.54 bsc - d3 -0.358-9.09 2 e 0.342 0.358 8.69 9.09 - e1 0.200 bsc 5.08 bsc - e2 0.100 bsc 2.54 bsc - e3 -0.358-9.09 2 e 0.050 bsc 1.27 bsc - e1 0.015 - 0.38 - 2 h 0.040 ref 1.02 ref 5 j 0.020 ref 0.51 ref 5 l 0.045 0.055 1.14 1.40 - l1 0.045 0.055 1.14 1.40 - l2 0.075 0.095 1.91 2.41 - l3 0.003 0.015 0.08 0.38 - nd 5 5 3 ne 5 5 3 n20 203 rev. 0 4/94 notes: 1. metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. symbol ?n? is the maximum number of terminals. symbols ?nd? and ?ne? are the number of terminals along the sides of length ?d? and ?e?, respectively. 4. the required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. the corner shape (square, notch, radius, etc.) may vary at the manufacturer?s option, from that shown on the drawing. 6. chip carriers shall be constructed of a minimum of two ceramic layers. 7. dimension ?a? controls the overall package thickness. the maxi- mum ?a? dimension is package height before being solder dipped. 8. dimensioning and tolerancing per ansi y14.5m-1982. 9. controlling dimension: inch. 10. materials: compliant to mil-i-38535. ceramic leadless chip carrier packages (clcc) spec number 511106-883
the information contained in this section has been developed through characterization by intersil semiconductor and is for use as application and design information only. no guarantee is implied. 198 design information february 2002 tm hfa1113 output limiting, ultra high speed programmable gain buffer amplifier typical performance curves v supply = 5v, r l = 100 ? , t a = +25 o c, unless otherwise specified small signal pulse response large signal pulse response small signal pulse response large signal pulse response small signal pulse response large signal pulse response a v = +2 200 150 100 50 0 -50 -100 -150 -200 output voltage (mv) 5ns/div a v = +2 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 output voltage (v) 5ns/div a v = +1 200 150 100 50 0 -50 -100 -150 -200 output voltage (mv) 5ns/div a v = +1 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 output voltage (v) 5ns/div a v = -1 200 150 100 50 0 -50 -100 -150 -200 output voltage (mv) 5ns/div a v = -1 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 output voltage (v) 5ns/div spec number 511106-883
design information (continued) the information contained in this section has been developed through characterization by intersil semiconductor and is for use as application and design information only. no guarantee is implied. 199 hfa1113 unclamped performance (a v = +2, v h = 2v, v l = -2v) clamped performance (a v = +2, v h = 1v, v l = -1v, 2x overdrive) frequency response frequency response for various load resistors frequency response for various load resistors frequency response for various load resistors typical performance curves v supply = 5v, r l = 100 ? , t a = +25 o c, unless otherwise specified (continued) in 0v to 0.5v a v = +2 out 0v to 1v 20ns/div in 0v to 1v a v = +2 out 0v to 1v 20ns/div gain (db) normalized 6 3 0 -3 -6 -9 0.3 1 10 100 1000 phase (degrees) frequency (mhz) v out = 200mv p-p a v = +2 0 -90 -180 -270 -360 gain phase a v = +1 a v = +2 a v = -1 a v = +1 a v = -1 gain (db) 0.3 1 10 100 1000 phase (degrees) frequency (mhz) 9 6 3 0 0 -90 -180 -270 -360 r l = 1k ? r l = 100 ? r l = 100 ? r l = 1k ? r l = 50 ? r l = 50 ? gain phase a v = +2, v out = 200mv p-p gain (db) 0.3 1 10 100 1000 0 -90 -180 -270 -360 phase (degrees) frequency (mhz) a v = +1, v out = 200mv p-p r l = 1k ? r l = 50 ? r l = 100 ? r l = 100 ? r l = 50 ? r l = 1k ? 6 3 0 -3 -6 -9 gain phase gain (db) 180 90 0 -90 -180 phase (degrees) 6 3 0 -3 -6 -9 a v = -1, v out = 200mv p-p r l = 1k ? r l = 50 ? r l = 100 ? r l = 100 ? r l = 50 ? r l = 1k ? 0.3 1 10 100 1000 frequency (mhz) gain phase spec number 511106-883
design information (continued) the information contained in this section has been developed through characterization by intersil semiconductor and is for use as application and design information only. no guarantee is implied. 200 hfa1113 frequency response for various output voltages frequency response for various output voltages frequency response for various output voltages full power bandwidth -3db bandwidth vs temperature gain flatness typical performance curves v supply = 5v, r l = 100 ? , t a = +25 o c, unless otherwise specified (continued) gain (db) 12 9 6 3 0 0 -90 -180 -270 -360 phase (degrees) a v = +2 4.0v p-p 2.5v p-p 1v p-p 1v p-p 4.0v p-p 2.5v p-p gain phase 0.3 1 10 100 1000 frequency (mhz) gain (db) 0 -90 -180 -270 -360 phase (degrees) 6 3 0 -3 -6 v out = 1v p-p v out = 2.5v p-p v out = 4v p-p v out = 1v p-p v out = 2.5v p-p v out = 4v p-p a v = +1 gain phase 0.3 1 10 100 1000 frequency (mhz) gain (db) 180 90 0 -90 -180 phase (degrees) 6 3 0 -3 -6 a v = -1 gain phase 0.3 1 10 100 1000 frequency (mhz) v out = 1v p-p v out = 2.5v p-p v out = 4v p-p v out = 1v p-p v out = 2.5v p-p v out = 4v p-p gain (db) normalized 15 12 9 6 3 0 -3 -6 -9 -12 -15 0.3 1 10 100 1000 frequency (mhz) v out = 5v p-p a v = +1 a v = +2 a v = -1 bandwidth (mhz) 900 850 800 750 700 650 600 550 500 -50 -25 0 +25 +50 +75 +100 +125 temperature ( o c) a v = -1 a v = +1 a v = +2 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 1 10 100 frequency (mhz) gain (db) normalized a v = -1 a v = +1 a v = +2 spec number 511106-883
design information (continued) the information contained in this section has been developed through characterization by intersil semiconductor and is for use as application and design information only. no guarantee is implied. 201 hfa1113 deviation from linear phase settling response low frequency reverse isolation (s 12 ) high frequency reverse isolation (s 12 ) 1db gain compression vs frequency 3rd order intermodulation intercept vs frequency typical performance curves v supply = 5v, r l = 100 ? , t a = +25 o c, unless otherwise specified (continued) 4 3 2 1 0 -1 -2 -3 -4 -5 -6 0 15 30 45 60 75 90 105 120 135 frequency (mhz) deviation (degrees) a v = -1 a v = +1 a v = +2 150 settling error (%) 0.6 0.4 0.2 0.1 0 -0.1 -0.2 -0.4 -0.6 -2 3 8 13 18 23 28 33 38 43 48 time (ns) a v = +2, v out = 2v -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 gain (db) 20 40 60 80 100 120 140 160 180 200 frequency (mhz) a v = +1 a v = -1 a v = +2 a v = +2 a v = -1 0 gain (db) -24 -30 -36 -42 -48 -54 -60 100 190 280 370 460 550 640 730 820 910 1000 frequency (mhz) phase (degrees) 180 135 90 45 0 a v = +1 a v = +2 a v = -1 gain phase a v = -1 a v = +1 a v = +2 output power at 1db compression (dbm) 20 18 16 14 12 10 8 6 4 2 0 100 200 300 400 500 frequency (mhz) a v = +1 a v = -1 a v = +2 30 20 10 0 intercept point (dbm) 100 200 300 400 2 - tone frequency (mhz) a v = -1 a v = +1 a v = +2 spec number 511106-883
design information (continued) the information contained in this section has been developed through characterization by intersil semiconductor and is for use as application and design information only. no guarantee is implied. 202 hfa1113 2nd harmonic distortion vs p out 3rd harmonic distortion vs p out 2nd harmonic distortion vs p out 3rd harmonic distortion vs p out 2nd harmonic distortion vs p out 3rd harmonic distortion vs p out typical performance curves v supply = 5v, r l = 100 ? , t a = +25 o c, unless otherwise specified (continued) -20 -30 -40 -50 -60 -70 -80 -90 -100 -6 -3 0 3 6 9 12 15 output power (dbm) distortion (dbc) a v = +2 100mhz 50mhz 30mhz -20 -30 -40 -50 -60 -70 -80 -90 -100 distortion (dbc) -6 -3 0 3 6 9 12 15 18 output power (dbm) a v = +2 100mhz 50mhz 30mhz -20 -30 -6 -3 0 3 6 9 12 15 distortion (dbc) output power (dbm) -40 -50 -60 -70 -80 -90 -100 a v = +1 100mhz 50mhz 30mhz distortion (dbc) a v = +1 100mhz 50mhz 30mhz -20 -30 -6 -3 0 3 6 9 12 15 output power (dbm) -40 -50 -60 -70 -80 -90 -100 distortion (dbc) -20 -30 -6 -3 0 3 6 9 12 15 output power (dbm) -40 -50 -60 -70 -80 -90 -100 100mhz 50mhz 30mhz a v = -1 distortion (dbc) -20 -30 -6 -3 0 3 6 9 12 15 output power (dbm) -40 -50 -60 -70 -80 -90 -100 100mhz 50mhz 30mhz a v = -1 spec number 511106-883
design information (continued) the information contained in this section has been developed through characterization by intersil semiconductor and is for use as application and design information only. no guarantee is implied. 203 hfa1113 integral linearity error overshoot vs input rise time overshoot vs input rise time overshoot vs input rise time supply current vs supply voltage supply current vs temperature typical performance curves v supply = 5v, r l = 100 ? , t a = +25 o c, unless otherwise specified (continued) -3.0 input voltage (v) -2.0 -1.0 0 +1.0 +2.0 +3.0 -0.04 -0.02 0 +0.02 +0.04 percent error (%) 100 300 500 700 900 1100 1300 overshoot (%) input rise time (ps) 60 50 40 30 20 10 0 v out = 0.5v a v = +1 a v = -1 a v = +2 100 300 500 700 900 1100 1300 overshoot (%) input rise time (ps) 60 50 40 30 20 10 0 v out = 1v a v = +1 a v = -1 a v = +2 60 50 40 30 20 10 0 100 300 500 700 900 1100 1300 overshoot (%) input rise time (ps) v out = 2v a v = +1 a v = -1 a v = +2 total supply voltage (v+ - v-, v) 22 17 15 13 11 supply current (ma) 59 9 7 5 678 10 21 20 19 6 8 10 12 14 16 18 25 24 23 22 21 20 19 18 17 16 15 -50 -25 0 +25 +50 +75 +100 +125 temperature ( o c) supply current (ma) spec number 511106-883
design information (continued) the information contained in this section has been developed through characterization by intersil semiconductor and is for use as application and design information only. no guarantee is implied. 204 hfa1113 output voltage vs temperature input noise characteristics non-linearity near clamp voltage (a v = -1) v h clamp accuracy vs overdrive v l clamp accuracy vs overdrive v h clamp accuracy vs overdrive typical performance curves v supply = 5v, r l = 100 ? , t a = +25 o c, unless otherwise specified (continued) 3.6 3.5 3.4 3.3 3.2 3.1 2.9 2.8 2.7 2.6 -50 -25 0 +25 +50 +75 +100 +125 temperature ( o c) output voltage (v) a v = -1 +v out (r l = 50 ?) |-v out | (r l = 100 ?) |-v out | (r l = 50 ?) 3.0 +v out (r l = 100 ?) 50 40 30 20 10 130 110 90 70 50 30 0.1 1 10 100 frequency (khz) noise voltage (nv/ hz ) 0 noise current (pa/ hz ) eni ini 20 15 10 5 0 -5 -10 -15 -20 v out - (a v * v in ) (mv) -3 -2 -1 0 1 2 3 a v * v in (v) v l = -3v v l = -1v v l = -2v v h = 3v v h = 1v v h = 2v 0 100 200 300 400 500 0 50 100 150 200 250 300 350 a v = 1 overdrive (% of v h ) clamp accuracy (mv) v h = 100mv v h = 2v v h = 1v v h = 500mv v l = 500mv 0 100 200 300 400 500 0 50 100 150 200 250 a v = 1 overdrive (% of v l ) clamp accuracy (mv) v l = 100mv v l = 1v v l = 2v v h = 500mv 0 100 200 300 400 500 0 100 200 300 400 a v = +2 overdrive (% of v h ) clamp accuracy (mv) v h = 100mv v h = 2v v h = 1v spec number 511106-883
design information (continued) the information contained in this section has been developed through characterization by intersil semiconductor and is for use as application and design information only. no guarantee is implied. 205 hfa1113 v l clamp accuracy vs overdrive overdrive recovery vs overdrive clamp accuracy vs temperature clamp bias current vs temperature v h clamp input bandwidth v l clamp input bandwidth typical performance curves v supply = 5v, r l = 100 ? , t a = +25 o c, unless otherwise specified (continued) 0 100 200 300 400 500 0 50 100 150 200 250 overdrive (% of v l ) clamp accuracy (mv) v l = 1v v l = 2v a v = +2 v l = 500mv v l = 100mv 100 200 300 400 500 0 500 1000 1500 2000 2500 3000 3500 overdrive level (% of clamp level) overdrive recovery time (ps) v h = 1v v h = 2v v h = 0.5v v h = 0.1v -50 0 +50 +100 +150 60 70 80 90 100 110 120 130 140 temperature ( c) clamp accuracy (mv) a v = -1, v in = 1.6v v h = 1v, v l = -1v v h v l +125 +75 +25 -25 -75 20 30 40 50 60 70 80 90 100 110 120 130 temperature ( c) clamp bias current ( a) v h = 1v, v l = -1v v l v h -50 0 +50 +100 +150 +125 +75 +25 -25 -75 frequency (mhz) 1 10 100 1000 v h = 600mv p-p v h = 1.2v p-p v h = 300mv p-p 6 3 0 -3 -6 -9 -12 gain (db) frequency (mhz) 1 10 100 1000 v l = 600mv p-p v l = 1.2v p-p v l = 300mv p-p 6 3 0 -3 -6 -9 -12 gain (db) spec number 511106-883
design information (continued) the information contained in this section has been developed through characterization by intersil semiconductor and is for use as application and design information only. no guarantee is implied. 206 hfa1113 application information closed loop gain selection the hfa1113 features a novel design which allows the user to select from three closed loop gains, without any external components. the result is a more flexible product, fewer part types in inventory, and more efficient use of board space. this ?buffer? operates in closed loop gains of -1, +1, or +2, and gain selection is accomplished via connections to the inputs. applying the input signal to +in and floating -in selects a gain of +1, while grounding -in selects a gain of +2. a gain of -1 is obtained by applying the input signal to -in with +in grounded. the table below summarizes these connections: pc board layout the frequency response of this amplifier depends greatly on the amount of care taken in designing the pc board. the use of low inductance components such as chip resis- tors and chip capacitors is strongly recommended, while a solid ground plane is a must! attention should be given to decoupling the power supplies. a large value (10 f) tantalum in parallel with a small value (0.1 f) chip capacitor works well in most cases. terminated microstrip signal lines are recommended at the input and output of the device. capacitance directly on the output must be minimized, or isolated as discussed in the next section. for unity gain applications, care must also be taken to minimize the capacitance to ground seen by the amplifier?s inverting input. at higher frequencies this capacitance will tend to short the -input to gnd, resulting in a closed loop gain which increases with frequency. this will cause excessive high frequency peaking and potentially other problems as well. an example of a good high frequency layout is the evalua- tion board shown in figure 2. driving capacitive loads capacitive loads, such as an a/d input, or an improperly terminated transmission line will degrade the amplifier?s phase margin resulting in frequency response peaking and possible oscillations. in most cases, the oscillation can be avoided by placing a resistor (r s ) in series with the output prior to the capacitance. gain (a cl ) connections +input (pin 3) -input (pin 2) -1 gnd input +1 input nc (floating) +2 input gnd figure 1 details starting points for the selection of this resis- tor. the points on the curve indicate the r s and c l combina- tions for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. r s and c l form a low pass network at the output, thus lim- iting system bandwidth well below the amplifier bandwidth of 850mhz. by decreasing r s as c l increases (as illus- trated in the curves), the maximum bandwidth is obtained without sacrificing stability. even so, bandwidth does decrease as you move to the right along the curve. for example, at a v =+1, r s =50 ? , c l = 30pf, the overall bandwidth is limited to 300mhz, and bandwidth drops to 100mhz at a v =+1, r s =5 ? , c l = 340pf. figure 1. recommended series output resistor vs. load capacitance evaluation board the performance of the hfa1113 may be evaluated using the hfa11xx evaluation board, slightly modified as follows: 1. remove the 500 ? feedback resistor (r2), and leave the connection open. 2. a. for a v = +1 evaluation, remove the 500 ? gain setting resistor (r1), and leave pin 2 floating. b. for a v = +2, replace the 500 ? gain setting resistor with a 0 ? resistor to gnd. the layout and modified schematic of the board are shown in figure 2. to order evaluation boards, please contact your local sales office. r s ( ? ) load capacitance (pf) 50 45 40 35 30 25 20 15 10 5 0 0 40 80 120 160 200 240 280 320 360 400 a v =+1 a v =+2 spec number 511106-883
design information (continued) the information contained in this section has been developed through characterization by intersil semiconductor and is for use as application and design information only. no guarantee is implied. 207 hfa1113 clamp operation general the hfa1113 features user programmable output clamps to limit output voltage excursions. clamping action is obtained by applying voltages to the v h and v l terminals (dip pins 8 & 5) of the amplifier. v h sets the upper output limit, while v l sets the lower clamp level. if the amplifier tries to drive the output above v h , or below v l , the clamp circuitry limits the output voltage at v h or v l ( the clamp accuracy), respec- tively. the low input bias currents of the clamp pins allow them to be driven by simple resistive divider circuits, or active elements such as amplifiers or dacs. clamp circuitry figure 3 shows a simplified schematic of the hfa1113 input stage, and the high clamp (v h ) circuitry. as with all current feedback amplifiers, there is a unity gain buffer (qx1 - qx2) between the positive and negative inputs. this buffer forces -in to track +in, and sets up a slewing current of: (v -in -v out )/r f +v -in /r g . this current is mirrored onto the high impedance node (z) by qx3-qx4, where it is converted to a voltage and fed to the output via another unity gain buffer. if no clamping is utilized, the high impedance node may swing within the limits defined by qp4 and qn4. note that when the output reaches it?s qui- escent value, the current flowing through -in is reduced to only that small current (-i bias ) required to keep the output at the final voltage. tracing the path from v h to z illustrates the effect of the clamp voltage on the high impedance node. v h decreases by 2v be (qn6 and qp6) to set up the base voltage on qp5. qp5 begins to conduct whenever the high impedance node reaches a voltage equal to qp5?s base voltage + 2v be (qp5 and qn5). thus, qp5 clamps node z whenever z reaches v h . r1 provides a pull-up network to ensure functionality with the clamp inputs floating. a similar description applies to the symmetrical low clamp circuitry controlled by v l . when the output is clamped, the negative input continues to source a slewing current (i clamp ) in an attempt to force the output to the quiescent voltage defined by the input. qp5 must sink this current while clamping, because the -in cur- rent is always mirrored onto the high impedance node. the clamping current is calculated as: i clamp =(v -in - v out clamped ) / 300 ? + v -in /r g . as an example, a unity gain circuit with v in = 2v, and v h = 1v, would have i clamp = (2v-1v) / 300 ? +2v/ = 3.33ma (r g = because -in is floated for unity gain applications). note that i cc will increase by i clamp when the output is clamp limited. clamp accuracy the clamped output voltage will not be exactly equal to the voltage applied to v h or v l . offset errors, mostly due to v be mismatches, necessitate a clamp accuracy parameter which is found in the device specifications. clamp accuracy is a function of the clamping conditions. referring again to figure 3, it can be seen that one component of clamp accuracy is the v be mismatch between the qx6 transistors, and the qx5 transistors. if the transistors always ran at the same current level there would be no v be mismatch, and no contribution to the inaccuracy. the qx6 transistors are biased at a constant current, but as described earlier, the current through qx5 is equivalent to i clamp . v be increases as i clamp increases, figure 2. evaluation board schematic and layout figure 3. hfa1113 simplified v h clamp circuitry v h +in v l v+ gnd 1 v- out bottom layout top layout 1 2 3 4 8 7 6 5 +5v 10 f 0.1 f v h 50 ? gnd gnd r1 -5v 0.1 f 10 f 50 ? in out v l (a v =+1) or 0 ? (a v =+2) +1 +in v- v+ qp1 qn1 v- qn3 qp3 qp4 qn2 qp2 qn4 qp5 qn5 z v+ -in v out i clamp r f = 300 ? (internal) qp6 qn6 v h r1 50k (30k for 300 ? v -in r g v l ) (internal) 200 ? spec number 511106-883
design information (continued) the information contained in this section has been developed through characterization by intersil semiconductor and is for use as application and design information only. no guarantee is implied. 208 hfa1113 causing the clamped output voltage to increase as well. i clamp is a function of the overdrive level (a vcl x v in -v out clamped ), so clamp accuracy degrades as the overdrive increases. as an example, the specified accuracy of 100mv for a 1.6x overdrive degrades to 240mv for a 3x overdrive. consideration must also be given to the fact that the clamp voltages have an affect on amplifier linearity. the ?nonlin- earity near clamp voltage? curve in the data sheet illus- trates the impact of several clamp levels on linearity. clamp range unlike some competitor devices, both v h and v l have usable ranges that cross 0v. while v h must be more positive than v l , both may be positive or negative, within the range restric- tions indicated in the specifications. for example, the hfa1113 could be limited to ecl output levels by setting v h = -0.8v and v l = -1.8v. v h and v l may be connected to the same voltage (gnd for instance) but the result won?t be a dc output voltage from an ac input signal. a 150 - 200mv ac signal will still be present at the output. recovery from overdrive the output voltage remains at the clamp level as long as the overdrive condition remains. when the input voltage drops below the overdrive level (v clamp / a vcl ) the amplifier will return to linear operation. a time delay, known as the over- drive recovery time, is required for this resumption of linear operation. the plots of ?unclamped performance? and ?clamped performance? highlight the hfa1113?s subnano- second recovery time. the difference between the unclamped and clamped propagation delays is the overdrive recovery time. the appropriate propagation delays are 8.0ns for the unclamped pulse, and 8.8ns for the clamped (2x overdrive) pulse yielding an overdrive recovery time of 800ps. the measurement uses the 90% point of the output transition to ensure that linear operation has resumed. note: the propagation delay illustrated is dominated by the fixtur- ing. the delta shown is accurate, but the true hfa1113 propagation delay is 500ps. spec number 511106-883 typical performance characteristics device characterized at: v supply = 5v, a v = +2v/v, r l =100 ? , unless otherwise specified. parameters conditions temperature typical units output offset voltage a v =+1, v cm =0v +25 o c8mv average offset voltage drift versus temperature full 10 v/ o c +input current a v =+1, v cm =0v +25 o c25 a +input resistance a v =+1, ? v cm =2v +25 o c50k ? -input resistance +25 o c300 ? +input noise voltage * f = 100khz +25 o c9nv/ hz +input noise current * f = 100khz +25 o c37pa/ hz input common mode range full 2.8 v input capacitance +25 o c2.2pf gain a v =+1, v in =2v +25 o c 0.99 v/v gain a v =+2, v in =1v +25 o c 1.98 v/v dc non-linearity * v out = 2v full scale +25 o c0.02% output voltage * a v =-1, r l =100 ? +25 o c 3.3 v a v =-1, r l =100 ? full 3.0 v output current * a v =-1, r l =50 ? +25 o c to +125 o c 60 ma a v =-1, r l =50 ? -55 o c to 0 o c 50 ma dc closed loop output resistance +25 o c0.3 ? quiescent supply current * r l = open full 24 ma -3db bandwidth * a v =-1, v out =200mv p-p +25 o c800mhz a v =+1, v out =200mv p-p +25 o c850mhz a v =+2, v out =200mv p-p +25 o c550mhz
design information (continued) the information contained in this section has been developed through characterization by intersil semiconductor and is for use as application and design information only. no guarantee is implied. 209 hfa1113 slew rate a v =-1, v out =5v p-p +25 o c2400v/ s a v =+1, v out =5v p-p +25 o c1500v/ s a v =+2, v out =5v p-p +25 o c1900v/ s full power bandwidth (note 1) a v =-1, v out =5v p-p +25 o c300mhz a v =+1, v out =5v p-p +25 o c150mhz a v =+2, v out =5v p-p +25 o c220mhz gain flatness (note 1) to 30mhz, a v =-1 +25 o c 0.02 db to 30mhz, a v =+1 +25 o c 0.10 db to 30mhz, a v =+2 +25 o c 0.015 db gain flatness (note 1) to 50mhz, a v =-1 +25 o c 0.05 db to 50mhz, a v =+1 +25 o c 0.20 db to 50mhz, a v =+2 +25 o c 0.036 db gain flatness (note 1) to 100mhz, a v =-1 +25 o c 0.10 db to 100mhz, a v =+2 +25 o c 0.07 db linear phase deviation (note 1) to 100mhz, a v =-1 +25 o c 0.13 degrees to 100mhz, a v =+1 +25 o c 0.83 degrees to 100mhz, a v =+2 +25 o c 0.05 degrees 2nd harmonic distortion (note 1) 30mhz, a v =-1, v out =2v p-p +25 o c-52dbc 30mhz, a v =+1, v out =2v p-p +25 o c-57dbc 30mhz, a v =+2, v out =2v p-p +25 o c-52dbc 3rd harmonic distortion (note 1) 30mhz, a v =-1, v out =2v p-p +25 o c-71dbc 30mhz, a v =+1, v out =2v p-p +25 o c-73dbc 30mhz, a v =+2, v out =2v p-p +25 o c-72dbc 2nd harmonic distortion (note 1) 50mhz, a v =-1, v out =2v p-p +25 o c-47dbc 50mhz, a v =+1, v out =2v p-p +25 o c-53dbc 50mhz, a v =+2, v out =2v p-p +25 o c-47dbc 3rd harmonic distortion (note 1) 50mhz, a v =-1, v out =2v p-p +25 o c-63dbc 50mhz, a v =+1, v out =2v p-p +25 o c-68dbc 50mhz, a v =+2, v out =2v p-p +25 o c-65dbc 2nd harmonic distortion (note 1) 100mhz, a v =-1, v out =2v p-p +25 o c-41dbc 100mhz, a v =+1, v out =2v p-p +25 o c-50dbc 100mhz, a v =+2, v out =2v p-p +25 o c-42dbc 3rd harmonic distortion (note 1) 100mhz, a v =-1, v out =2v p-p +25 o c-55dbc 100mhz, a v =+1, v out =2v p-p +25 o c-49dbc 100mhz, a v =+2, v out =2v p-p +25 o c-62dbc typical performance characteristics (continued) device characterized at: v supply = 5v, a v = +2v/v, r l =100 ? , unless otherwise specified. parameters conditions temperature typical units spec number 511106-883
design information (continued) the information contained in this section has been developed through characterization by intersil semiconductor and is for use as application and design information only. no guarantee is implied. 210 hfa1113 3rd order intercept (note 1) 100mhz +25 o c28dbm 300mhz +25 o c13dbm 1db compression (note 1) 100mhz +25 o c19dbm 300mhz +25 o c12dbm reverse isolation (s 12 ) (note 1) 40mhz +25 o c-70db 100mhz +25 o c-60db 600mhz +25 o c-32db rise and fall time a v =-1, v out =0.5v p-p +25 o c500ps a v = + 1, v out =0.5v p-p +25 o c480ps a v =+2, v out =0.5v p-p +25 o c700ps overshoot (note 1) a v =-1, v out =0.5v p-p +25 o c12% a v =+1, v out =0.5v p-p +25 o c45% a v =+2, v out =0.5v p-p +25 o c6% settling time (note 1) a v = +2, to 0.1%, v out = 2v to 0v +25 o c13ns a v = +2, to 0.05%, v out =2v to 0v +25 o c20ns a v = +2, to 0.02%, v out =2v to 0v +25 o c36ns differential gain a v =+2, r l =150 ? , ntsc +25 o c0.02% differential phase a v =+2, r l =150 ? , ntsc +25 o c 0.04 degrees overdrive recovery time, (2x overdrive) v in = 1v, v h =+1v, v l =-1v +25 o c0.75ns clamp accuracy a v =-1, v in = 1.6v, v h =+1v, v l =-1v +25 o c 100 mv clamped overshoot v in = 1v, v h =+1v, v l =-1v, input t r /t f =2ns +25 o c7% negative clamp range (v l )+25 o c -5.0 to +2.0 v positive clamp range (v h )+25 o c -2.0 to +5.0 v clamp input bias current v h =+1v, v l =-1v +25 o c50 a clamp input bandwidth v in = 100mv, v h or v l =100mv p-p +25 o c500mhz note: 1. see typical performance curves for more information. typical performance characteristics (continued) device characterized at: v supply = 5v, a v = +2v/v, r l =100 ? , unless otherwise specified. parameters conditions temperature typical units spec number 511106-883 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certification. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by int ersil is believed to be accurate and reli- able. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents o r other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its sub sidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com

▲Up To Search▲

Price & Availability of HFA1113ML883

	To Download HFA1113ML883 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .